1. Field
Exemplary embodiments of the present invention relate to a semiconductor fabrication technology, and more particularly, to a method for fabricating a semiconductor device employing a metal electrode containing carbon and nitrogen.
2. Description of the Related Art
As a semiconductor device such as a dynamic random access memory (DRAM) gradually operates at a high speed, a P-type metal oxide semiconductor field effect transistor (PMOSFET) and an N-type metal oxide semiconductor field effect transistor (NMOSFET) operating at high speeds are used. To ensure that the NMOSFET and the PMOSFET have proper characteristics while operating at a high speed, a gate electrode of the NMOSFET and a gate electrode of the PMOSFET are to have adequate work functions, respectively. Here, a work function of the gate electrode of the NMOSFET is close to a silicon conduction-band edge energy level and a work function of the gate electrode of the PMOSFET is close to a silicon valence-band edge energy level. In such a case, the channels of the NMOSFET and the PMOSFET may be formed of a surface channel. Thus, the NMOSFET and the PMOSFET may operate at a high speed.
FIG. 1 is a diagram illustrating the structure of a conventional semiconductor device.
Referring to FIG. 1, an isolation layer 12 is formed in a semiconductor substrate 11 to define an NMOSFET region and a PMOSFET region in the semiconductor substrate 11.
A first gate 101 is formed on the NMOSFET region and a second gate 102 is formed on the PMOSFET region. The first gate 101 is obtained by stacking a silicon oxide layer (SiO2) 13A, an N+ polysilicon layer (N+ Poly-Si) 14A, and a tungsten layer (W) 15A. The second gate 102 is obtained by stacking a silicon oxide layer (SiO2) 13B, a P+ polysilicon layer (P+ Poly-Si) 14B, and a tungsten layer (W) 15B.
In the above-mentioned conventional semiconductor device, the silicon oxide layers 13A and 13B used as a gate dielectric layer are grown to have a thickness of 30 Å or less in order to increase a driving current. However, a leakage current value is increased due to a direct tunneling phenomenon. Therefore, off-state characteristics may deteriorate.
Furthermore, in the conventional semiconductor device, in order to form the N+ polysilicon layer 14A and the P+ polysilicon layer 14B, since a polysilicon layer is deposited, a lithography process is performed twice, an ion implantation process is performed, and thus, the fabrication process becomes complicated.
Here, dopant, for example, boron, doped on the P+ polysilicon layer 14B penetrates into the silicon oxide layer 13B serving as a lower gate dielectric layer, resulting in an increase in a leakage current.
Since a gate electrode is formed of a polysilicon layer doped with N type and p type impurities, resistivity is high. Also, since a depletion region is formed in the gate electrode, the operation speed thereof may decrease.